RISC-V /Debug /External Trigger (64-bit tmexttrigger)

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Interpret as External Trigger (64-bit tmexttrigger)

63 6059 5655 5251 4847 4443 4039 3635 3231 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (breakpoint)action0select0 (intctl)intctl 0 (hit)hit 0 (dmode)dmode 0type

action=breakpoint

Description

This register provides access to the trigger selected by {csr-tselect}. The reset values listed here apply to every underlying trigger.

This register is accessible as {csr-tdata1} when {tdata1-type} is 7.

This trigger fires when any selected TM external trigger input signals. Up to 16 TM external trigger inputs coming from other blocks outside the TM, (e.g. signaling an hpmcounter overflow) can be selected. Hardware may support none or just a few TM external trigger inputs (starting with TM external trigger input 0 and continuing sequentially). Unsupported inputs are hardwired to be inactive.

If the trigger fires with {tmexttrigger-action}=0 then zero is written to the tval CSR on the breakpoint trap. This trigger fires asynchronously but it is subject to delegation by medeleg[3] like the other triggers.

The TM external trigger input can signal when the trigger is prevented from firing due to one of the mechanisms in nativetrigger. An implementation may either ignore the signal altogether when it cannot fire (dropping the trigger event) or it may hold the action as pending and fire the trigger once it is legal to do so.

đź“Ś NOTE

{tmexttrigger-intctl} is intended to be used by the clicinttrig mechanism from the Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extensions.

Fields

action

The action to take when the trigger fires. The values are explained in tab:action.

0 (breakpoint):

1 (debug mode):

2 (trace on):

3 (trace off):

4 (trace notify):

8 (external0):

9 (external1):

select

Selects any combination of up to 16 TM external trigger inputs that cause this trigger to fire.

intctl

This optional bit, when set, causes this trigger to fire whenever an attached interrupt controller signals a trigger.

hit

If this bit is implemented, the hardware sets it when this trigger matches. The trigger’s user can set or clear it at any time. It is used to determine which trigger(s) matched. If the bit is not implemented, it is always 0 and writing it has no effect.

dmode
type

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